In order to retain data written to dynamic memory cells, semiconductor memory, such as dynamic random access memory (DRAM), may perform a periodic refresh operation. In addition, the data retention characteristics of dynamic memory cells may worsen with increasing chip temperature. For this reason, when the chip temperature is high, the refresh cycle is shortened.
For example, Japanese Laid-Open Patent Publication No. 2003-115189 discloses a controller that controls the operation of semiconductor memory. By monitoring a self-refresh from the semiconductor memory, the controller may adjust the generation cycle of a refresh request signal that is supplied to the semiconductor memory. In other examples, Japanese Laid-Open Patent Publication Nos. 2002-140891, 11-31383, and 11-273340 disclose technology wherein, given a correlation between the clock cycle and the chip temperature, the refresh cycle may be shortened when the clock cycle is short and the chip temperature is high.
For example, in semiconductor memory that generates a refresh request signal using a clock signal, the generation cycle of the refresh request signal may be lengthened when the clock cycle lengthens. When the clock cycle is set long, the refresh interval of the dynamic memory cells lengthens, which may make data retention problematic.